LOGIC SYNTHESIS OF VLSI CIRCUITS

Electrical Engineering 318

Computer Science 316

Tajana Simunic

This directory contains general material for EE318

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This URL contains lecture notes and homeworks. Lecture notes are made avialable as they get ready. Homework solutions are not posted here.

Every student should register at EE Class. All grades, HW and exam solutions will be posted there.

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• General Information
• Course Description
• Required EE Class Registration
• Course Schedule
• Errata corrige (based on textbooks' 4th print)
• Introduction (Lecture 1)
• Two-level logic optimization (Lectures 2 and 3 )
• Homework 1 (Due Jan. 28th, 2:15pm)
• Review Session (Review 1)
• Data structures for logic optimization (Lecture 4)
• Heuristic two-level logic optimization (Lecture 5)
• Homework 2 (Due Feb. 4th, 2:15pm)
• Binary Decision Diagrams (Lecture 6)
• ICCAD 95 Paper: Binary Decision Diagrams and Beyond by R. Bryant (Lecture 6 supplement)
• Review Session (Review 2)
• Symbolic minimization and encoding problems (Lecture 7)
• Midterm Info
• TA Evaluation - earn easy 5 bonus points!
• Homework 3 (Due Feb. 25th, 2:15pm)
• Homework 3 part 2
• Homework 3 Submission Instructions
• Review Session (Review 3)
• Multilevel Logic Synthesis (Lecture 8)
• Algebraic Methods (Lecture 8)
• Boolean Methods (Lecture 9)
• Review Session (Review 4)
• Timing Issues in ML Synthesis (Lecture 10)
• Review Session (Review 5)
• Homework 4 (Due March 6th, 2:15pm)
• Retiming (Lecture 11)
• Synchronous Logic Optimization (Lecture 12)
• Review Session (Review 6)
• Architectural synthesis overview (Lecture 13)
• System C (Lecture 14)
• Homework 5 (Due March 13th, 2:15pm)
• Library Binding (Lecture 15)
• Library Binding Update (Lecture 15)
• Review Session (Review 7)
• Final Info