- Olympus Synthesis System (Stanford U.): synthesis from HardwareC (HDL with C-like syntax and cycle-based semantic)
- Cosyma (Braunschweig TU): synthesis of co-processor from C*
- SpC (Stanford U.): Synthesis of Pointers in C
- Other related projects:
- SUIF (Stanford U.): compiler framework
- PAM-Blox (Stanford U.): object-oriented design environment for FPGA
- Splash 2 Processor: Data Parallel C on a Reconfigurable Logic Array
- BRASS (UC Berkeley): Automatic C Compilation for Garp
- RAW Compiler (MIT): compiler for the distributed RAW architecture
- Transmogrifier C: compiler for a simple hardware description language
- Matisse Project (Imec): research project on a compiler for networking applications
- OCAPI (Imec): object-oriented circuit generators for ASICs
- SpecC (UC. Irvine): the SpecC language for system modeling (also in SpecC Technology Open Consortium)
- Fridge: Fixed-point pRogrammIng DesiGn Environment
- Handle-C
- Cadence: VCC (Felix), ECL (Esterel-C Language)
- C Level Design Inc. (formerly CompiLogic Corporation): C2HDL
- Co-Design Automation: Superlog (S2K)
- CoWare: N2C
- CynApps (formerly C2 Design Automation)
- EtherDesign Software
- Frontier Design: A|RT Builder
- LavaLogic: Forge (initially synthesis from Java)
- Synopsys:
CoCentric SystemC Compiler
,
SystemC (formerly known as Scenic/Scenery),
Nimble
- Other related projects:
- TransModeling Inc.
- Simulation Magic Inc.
- Celoxica (formerly Embedded Solutions): Handle-C
- Easics
[1998] [1999] [2000]
- C Level fields C++ class library in EE Times January 00
- Cadence adds system-level design tool to EDA flow in EE Times January 00
- TransModeling tool supports SystemC in EE Times January 00
- Verilog creator joins tool startup in EE Times January 00
- CoWare licenses Ocapi C/C++ from IMEC in EE Times February 00
- Three EDA startups score venture funding in EE Times February 00
- LavaLogic to field Java-based synthesis tool in EE Times March 00
- Frontier refines C-based synthesis tool in EE Times March 00
- SpecC opens dialogue with SystemC camp in EE Times March 00
- Synopsys spins system-level modeling, validation tool in EE Times March 00
- SystemC 1.0 available for download in EE Times March 00
- SystemC support set for launch at DSP World in EE Times April 00
- Cambridge startup claims speedier simulation tools in EE Times April 00
- Co-Design launches multilingual system design tools in EE Times May 00
- NEC Electronics tips high-level design initiative in EE Times May 00
- Get2Chip tips comprehensive synthesis tool in EE Times June 00
- Cadence joins Open SystemC Initiative in EE Times June 00
- Accellera wants to standardize C/C++ design language in EE Times June 00
- Panel weighs hardware, software design options in EE Times June 00
- Rivalry threatens C/C++ initiative in EE Times June 00
-
Xilinx buys system-level synthesis tool for FPGA suite
in EE Times July 00
-
ESNUG report turns up DAC surprises
in EE Times July 00
- DATE00: Technical Sessions 6A: hot topic: Hardware synthesis from C/C++ models
- DATE00: 2A EMBEDDED TUTORIAL - System Level Design Using C++, 3E Innovative Topics in Design Methodologies, 5A Architectural-Level Synthesis
- DAC00: Session 25 Panel: the future of system design languages