CSL - Stanford University DEIS - University of Bologna
PPP
Description of the main Tools
PPP File Tranfer PPP Synthesis PPP Optimization PPP Simulation
File Transfer
The file transfer in PPP is based on the FTP protocol. The user can upload the input files on the server and dowload the final results or the status logs. Recent browsers (such as Netscape v.2 and above) fully support upload and download based on anonymous FTP. If the browser does not support bidirectional FTP connection, the traditional Unix' ftp command can be used to perform file transfer. Notice that each user in PPP has a disk quota. If the quota is exceeded on the server the user session will be terminated. This is a form of protection against excessive usage of servers' disk space. The default user quota is 20Mb.

Synthesis for Low Power
The synthesis tool in PPP performs automatic Gated-Clock generation, using the algorhitms presented by Benini et. al. The starting point for synthesis is the FSM specfication in kiss2 format.
The tool finds idle conditions where the clock can be safely stopped without compromising the functionality (while saving power). If the FSM is a Mealy machine, it is automatically transformed in a functionally equivalent FSM for which self-loop extraction is more profitable. A complete path from synthesis to accurate power estimation is implemented in PPP. The power dissipation of the gated clock implementations is automatically estimated, and the best solution is chosen.
The output provided by synthesis is a mapped verilog netlist that implements thespecification with reduced power consumption. The user can simulate the netlist using the gate-level simulator in PPP.

Power Optimization
The optimization embedded in PPP targets the minimization of the peak current for sequential circuits based on edge-triggered flip-fliop (with a single clock). The circuit is initially specified in slif.
The peak current minimization is based on the algorithms presented by Vuillod et al.: clock skew is constructively exploited to reduce the number of events (and dynamic current) synchronized with the clock. It is possible to specify the number of clock drivers allowed in the circuit and generate a clustered solution (only NP different skews are allowed, where NP is the number of clock drivers).
A mapped circuit and the clock skew values are the final outputs of the optimization phase. The quality of the results is estimated and validated exploiting the accurate current estimation capablities of the gate-level power simulator within PPP.

Power Simulation
PPP embeds an accurate simulator for power and current estimation that operates at the gate level. It is based on the symbolic model of CMOS gates proposed by A. Bogliolo et. al.. The simlator has accuracy close to electical simulation and speed similar to traditional gate-level simulators.
The input of PPP is a mapped verilog netlist. Hierarchical verilog descriptions are supported as long as the leaf cells are pre-characterized library elements. The output of the simulator are power statistics, current waverforms and average/istantaneous power/energy dissipation data. Currently only one library has been fully characterized and can be used for power estimation.
The simulator is used for estimation and validation during gated-clock synthesis and clock skew optimization, the other two main features embedded in PPP.
Alessandro Bogliolo
Luca Benini
Patrick Vuillod 		alex@konishiki.stanford.edu
luca@pampulha.stanford.edu
vuillod@coolidge.stanford.edu