KISS
A sequential circuit can be specfied as a finite-state machine (FSM). The FSM
description format assumes symbolic names for the state (pre-encoding), while
inputs and outpus are specified with cube notation, usign the three
symbols 1, 0, and - (don't care). Kiss is a tabular format. Each row in the
table has four entries: input field, present state field, next state field
and output field. There are as many rows as transitions in the state graph
of the FSM.
BLIF
The goal of BLIF (Berkeley Logic Interchange Format) is to describe a
logic-level circuit in textual form.
A circuit is a combinational or sequential network of
logic functions. It can be viewed as a directed graph of combinational logic
nodes and sequential logic elements. Each node has a single-output logic
function associated with it. Each feedback loop must contain at least one
latch (flip-flop). Each net (or signal) has only a single driver, and either
the signal or the gate wich drives the signal can be named without ambiguity.
SLIF
SLIF is a concise format used to describe a stuctural view of logic circuits
andtheir interconnections.
It is a hierarchiacal notation that is described in ASCII files.
Each SLIF statement is terminated by a semicolon. Statements may appear
in any order within the description of a model, with the restriction that
inputs and outputs must be declared before they are used and that the last
statement in a model description must be the .endmodel statement.
For more information on Blif, Kiss and Slif see the "Logic Synthesis and
Optimization Benchmarks User Guide", version 3.0 by Seeyang Yang, MCNC.
PPP does not accept the full BLIF, KISS and SLIF sintax. In particular,
hierarchical descriptions are not supported. Attributes are ignored.
It is assumed that a netlist describes an unmapped, flattened sequential
network. The '*' placeholder is the only unuspported feature in KISS.